1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to the test and debug of asynchronous pipelines used to convey information in electronic circuits.
2. Description of the Related Art
Many modern digital circuits are synchronous circuits. Synchronous digital circuits typically include storage elements such as flip-flops or latches that move data based on the edge (or edges) of a reference clock signal.
More recently, the use of asynchronous (i.e. clockless) circuits has increased. Asynchronous circuits may enable much faster operating speeds, and may also allow for reduced power consumption and reduced electromagnetic radiation due to the lack of a reference clock signal. Instead of relying on a reference clock, asynchronous circuits may be implemented as data pipelines and rely on local coordination control circuits to ensure an orderly flow through the pipelines.
FIG. 1 is a block diagram of one embodiment of a clockless pipeline. In the embodiment shown, the clockless pipeline includes a plurality of control circuits (‘ctrl’) coupled to each other by a signal line for conveying clockless control signals. Each control circuit is coupled to a respective latch logic circuit (‘LL’) via a driver. Combinational logic circuits (‘CL’) are coupled between the latch logic circuits. A data path extends through latch logic and combinational logic circuits.
The control circuits in the embodiment of FIG. 1 are configured to exchange control signals with each other. When a given stage is ready to receive data, its respective control circuit sends an acknowledgement signal to the control circuit of the previous pipeline stage indicating that the stage is empty and ready to receive data. If data is present in the previous pipeline stage, a request signal is sent back to the originating control circuit. Responsive to receiving this request signal, the control circuit drives a signal to the latch logic (via the driver), which causes data to be latched in and allows it to propagate to the combinational logic. This effectively provides a local clock pulse or strobe to the latch logic, and this pulse is active only when required to latch data.
After latching the data to the combinational logic, the control circuit of the given stage will remain idle until it receives a signal from the control circuit of the next stage indicating that the next stage is ready to receive data. Responsive to receiving this signal, a request signal is sent to the next stage control circuit and data is latched into the next stage responsive thereto.
In summary, data can be latched to a next stage in the pipeline when there is valid data in front of the next stage latch logic, and when the next stage is empty. If the next stage is not empty, the pipeline will stall until such time as the next stage becomes empty and can thus receive data. The control circuits of the pipeline work together in the described manner to coordinate the movement of data from one stage to another without the need for a reference clock signal.
While many synchronous circuits can be tested by applying test patterns and unloading test response data via scan chains, traditional scan-based testing cannot be applied to asynchronous circuits. In order to test clockless pipelines such as that described above, the various circuits must be modified. The added circuitry may include extra latches and multiplexers and may consume a significant amount of circuit area, and can also cause greater power consumption.